Wednesday, January 8, 2014

Well, I've neglected TI stuff for long enough, it's time to get back into it. What took so long was knowing that the first thing I would have to tackle would be the dreaded word-byte conversion problem. This is a ridiculously stubborn problem, and one I've been fighting with since I started this. Ugh.

I'm trying something new here. The idea is to use an UNSPEC instruction to encode a subreg expression. This would be used to tell the compiler "The value is magically converted to byte representation". I assume the UNSPECs will not be disappeared by reload, and the existing code should split expressions like the one I've been fighting with.

For reference, here's the unmodified output from reload:

Reloads for insn # 9
Reload 0: reload_in (QI) = (reg:QI 1 r1)
        reload_out (QI) = (reg:QI 1 r1 [orig:21 D.1197 ] [21])
        PC_REGS, RELOAD_OTHER (opnum = 0), can't combine
        reload_in_reg: (subreg:QI (reg:HI 1 r1 [25]) 1)  <-- br="" is="" this="" want="" we="" what="">        reload_out_reg: (reg:QI 1 r1 [orig:21 D.1197 ] [21])  <-- br="" expression="" good="" lost="" no="" subreg="">        reload_reg_rtx: (reg:QI 1 r1 [orig:21 D.1197 ] [21])

Apparently, a naive replacement of the subreg expression with (unspec:QI [(reg:HI 1 r1 [25])] 1) is a dismal failure. There is a sanity check elsewhere in reload that fails, since I'm trying to replace a register location with an undefined action. I may have to split up the original expression somehow. What would that look like?

Oh yeah, I did this before:
(set (reg:QI 1 r1)
        (subreg:QI (reg:HI 1 r1) 1))
(set (reg:QI 1 r1)
        (plus:QI 1 r1)
            (const_int 48 [0x30]))) 59 {addqi3} (nil))

Finding a way to do this in general will be tricky. Even assuming simple expressions, we could have things like:
(set ( ))
(set ( ))
(set ( ))
(set ( ))
(set ( ))
(set ( ))
(set ( ))
(set ( ))

Each of these need seperate splitting. As bad as this is, it could get so much more complicated. So apparently, splitting is no good. I guess I can try to put more effort into the unspec route.

After beating on GCC for a while, I finally got a compile to complete with unspec instructions, but it's not pretty:
        div  r3, r1            # Modulo is in R2
        mov  r2, r1            # Move result to R1
        movb r1, r2            # Wait a sec, this should be like "swpb r2"
        ai   r2, >3000         # Add '0' to result in byte mode
        fake_set_subreg r1 r2  # This fake insn is like "swpb r2; movb r2, r1", makes no sense here
        movb r1, @>8C00        # Copy to VDPWD
        b    *r11

I'm backing all this out, it won't work.

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